1. Field of Invention
The disclosure generally relates to chip package interactions (CPIs) between a chip carrier and a silicon chip in a flip chip ball grid array package. More particularly, the disclosure relates to providing an elastic modulus map of a chip carrier that identifies probable mechanical failure sites during chip join and cool-down of the flip chip package.
2. Description of Related Art
The semiconductor marketplace continues to demand smaller devices, which require greater connectivity densities for packaging design. The increased functionality of smaller semiconductor devices requires an increased number of signal, power, and ground connections, and a corresponding decrease in connection pitch is required to maintain reasonable chip size. The combination of these requirements results in greater complexity of semiconductor packaging design.
Referring to FIG. 1, the packaging design requirement is especially critical in flip chip ball grid array packages, where demand for a greater density of connections must coexist with good electrical and thermal reliability performance. When compared to other packaging technologies, flip chip packaging significantly increases the number of signal, power and ground connections of the silicon chip that are connected to the chip carrier through solder bumps or controlled collapse chip connections (C4s). During chip join and cool down, the solder bumps will form electrical and mechanical connections between flip chip (FC) pads on the surface of the chip carrier. In turn, the FC pads will electrically connect through various pathways of the chip carrier to, for example, ball grid array, lands and solder balls that connect to the system board.
FIG. 2 illustrates a cross section of a chip carrier, upon which FC pads have not yet been formed. The chip carrier usually includes one or more laminated core layers and several build-up layers. Each of the core layers includes a dielectric 210 and can include one or more conductive planes 220, such as metal fills, for power and ground. Core dielectrics can comprise any of ceramics, plastics and organic materials. Various core layers can also include conductive signal lines 230, such as metal signal lines. In some case, the core layers can be penetrated by a plated through hole via 260 that has a peripheral conductive metal layer, which surrounds a non-conductive epoxy resin core. The build-up layers also include a dielectric material 240 and can further include any of conductive planes and conductive signal lines. A laser-drilled or blind via 250 can penetrate a build-up layer. Upon adding finishing layers, FC pads can be located in areas 280 between insulators 270 formed on the outer surface of the build-up layer.
The mechanical stresses and strains that occur with chip package interactions (CPIs) are complex, depending upon many factors including chip carrier design, silicon chip design, process variations in chip carrier and silicon chip manufacture, and process variations in bond and assembly. Many CPIs result from stress/strain caused by a mismatch between the coefficients of thermal expansion (CTE) of the chip carrier and the silicon chip during the processes of heating the solder bumps or C4 connections to their melting point and the subsequent cooling of the joined chip carrier and silicon chip to an ambient temperature. Differences in contraction during chip-join and cool-down result in shear forces being applied between the chip carrier and the silicon chip. These shear forces are usually propagated as stress/strain through the solder bumps to an interface region of the solder bump with the silicon chip.
One type of chip package interaction (CPI) is a so-called “white bump” because of the white area produced on photographically processed acoustic images during test of the flip chip package. Each white bump corresponds to the location of a material fracture, i.e., a test failure, in the interface region between the solder bump and the silicon chip. White bumps typically occur during chip join and cool-down, or during subsequent handling of the flip chip package before an underfill is introduced between the chip carrier and the silicon chip to more uniformly distribute stresses across the chip carrier/silicon chip interface.
Experimental results indicate that white bumps are more likely to occur at sites associated with a greater shear force and/or a greater stiffness of materials. Mechanical analysis indicates that the shear forces produced at the FC pads on the chip carrier are proportional to a radial distance from a centrally neutral point on the chip carrier, i.e., a point that does not move with either thermal expansion or contraction of the chip carrier. The elastic modulus (Young's modulus) or the stiffness of the chip carrier depends on the stiffness of the layers comprising the chip carrier. Each layer, when viewed in a plan view, can vary in stiffness across its area, depending on the design elements e.g., dielectrics, power planes or fills, signal lines or wires, and vias, disposed within any of the layers of the chip carrier.
There remains a need for a method to identify those design elements of a chip carrier of a flip chip package that can contribute to possible “white bump” failures in the flip chip package, based on elastic modulus mapping of the design elements disposed within the chip carrier of the flip chip package, and to modify these design elements to decrease the probability of such “white bump” failures.